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Integrated Circuit Systems, Inc.
ICS950201
Programmable Timing Control HubTM for P4TM
Recommended Application: CK-408 clock for Intel(R) 845 chipset with P4 processor. Output Features: * 3 Differential CPU Clock Pairs @ 3.3V * 7 PCI (3.3V) @ 33.3MHz * 3 PCI_F (3.3V) @ 33.3MHz * 1 USB (3.3V) @ 48MHz * 1 DOT (3.3V) @ 48MHz * 1 REF (3.3V) @ 14.318MHz * 5 3V66 (3.3V) @ 66.6MHz * 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz Features: * Supports spread spectrum modulation, down spread 0 to -0.5%. * Efficient power management scheme through PD#, CPU_STOP# and PCI_STOP#. * Uses external 14.318MHz crystal * Stop clocks and functional control available through I2C interface. Key Specifications: * CPU Output Jitter <150ps * 3V66 Output Jitter <250ps * CPU Output Skew <100ps, programmable over 800 ps with groups CPU0,1 and CPU2.
Pin Configuration
56-Pin SSOP & TSSOP
* These inputs have 150K internal pull-up resistor to VDD.
Block Diagram
Frequency Table
FS2 FS1 FS0 0 0 0 0 Mid Mid Mid Mid 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CPU (MHz) 66.66 100.00 200.00 133.33 Tristate TCLK/2 3V66 (MHz) 66.66 66.66 66.66 66.66 Tristate TCLK/4 66Buff[2:0] 3V66[4:2] (MHz) 66.66 66.66 66.66 66.66 Tristate TCLK/4 PCI_F PCI (MHz) 33.33 33.33 33.33 33.33 Tristate TCLK/8 Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved
0460G--08/31/04
Integrated Circuit Systems, Inc.
ICS950201
Pin Description
PIN NUMBER
1, 8, 14, 19, 26, 32, 37, 46, 50 2 3 7, 6, 5 4, 9, 15, 20, 27, 31, 36, 41, 47 18, 17, 16, 13, 12,11, 10 24,23, 22, 21 24 25
PIN NAME
VDD X1 X2
TYPE
PWR 3.3V power supply
DESCRIPTION
X2 Cr ystal 14.318MHz Cr ystal input Input X1 Cr ystal 14.318MHz Cr ystal output Output
PCICLK_F (2:0)
GND PCICLK (6:0) 3V66 (5:2) 3V66_5 PD#
OUT
PWR OUT OUT OUT IN
Free running PCI clock not affected by PCI_STOP# for power management.
Ground pins for 3.3V supply PCI clock outputs 66MHz reference clocks, from internal VCO 66MHz reference clock, from internal VCO Invokes power-down mode. Active Low.
28
Vtt_PWRGD#
IN I/O IN
OUT IN OUT OUT OUT IN OUT IN OUT OUT IN IN OUT
This 3.3V LVTTL input is a level sensitive strobe used to determine when FS(2:0) and MULTISEL0 inputs are valid and are ready to be sampled (active low) Data pin for I2C circuitry 5V tolerant Clock pin of I2C circuitry 5V tolerant
66MHz reference clocks, from internal VCO Halts PCICLK clocks at logic 0 level, when input low except PCICLK_F which are free running 3.3V output selectable through I2C to be 66MHz from internal VCO or 48MHz (non-SSC) 48MHz output clock for DOT 48MHz output clock for USB Special 3.3V input for Mode selection, cannot be logic 1 This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 3.3V LVTTL input for selecting the current multiplier for CPU outputs "Complementor y" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. "True" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. Halts CPUCLK clocks at logic 0 level, when input low Frequency select pins 14.318MHz reference clock.
29 30 33 34 35 38 39 40 , 42 43 44, 48, 51 45, 49, 52 53 55, 54 56
SDATA SCLK 3V66_0 PCI_STOP# 3V66_1/VCH_CLK 48MHz_DOT 48MHz_USB FS2 I REF MULTSEL0 CPUCLKC (2:0) CPUCLKT (2:0) CPU_STOP# FS (1:0) REF
Power Groups (Analog)
VDDA = Analog Core PLL1 VDDREF = REF, Xtal VDD48 = 48MHz, PLL
0460G--08/31/04
(Digital)
VDDPCI VDD3V66 VDDCPU
2
Integrated Circuit Systems, Inc.
ICS950201
Truth Table
FS2 0 0 0 0 Mid Mid Mid Mid FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 CPU (MHz) 66.66 100.00 200.00 133.33 Tristate TCLK/2 3V66 (5:0) (MHz) 66.66 66.66 66.66 66.66 Tristate TCLK/4 PCI_F PCI (MHz) 33.33 33.33 33.33 33.33 Tristate TCLK/8 Reserved Reserved REF0 (MHz) 14.318 14.318 14.318 14.318 Tristate TCLK Reserved Reserved USB/DOT (MHz) 48.00 48.00 48.00 48.00 Tristate TCLK/2 Reserved Reserved
Reserved Reserved Reserved Reserved
Maximum Allowed Current
Max 3.3V supply consumption Max discrete cap loads, Vdd = 3.465V All static inputs = Vdd or GND 40mA 360mA
Condition Powerdown Mode (PWRDWN# = 0) Full Active
Host Swing Select Functions
Board Target Trace/Term Z 50 ohms Reference R, Iref = VDD/(3*Rr) Rr = 475 1%, Iref = 2.32mA Output Current Ioh = 6* I REF
MULTISEL0
Voh @ Z
1
0.7V @ 50
0460G--08/31/04
3
Integrated Circuit Systems, Inc.
Byte 0: Control Register
ICS950201
Bit Bit 0 Bit 1 Bit 2
Pin# 54 55 40
Name FS0 FS1 FS2
PWD2 X X X X
Type1 R R R R RW R RW
Bit 3
34
PCI_STOP#
3
1 Bit 4 Bi t 5 Bit 6 Bit 7 53 35 Spread Enabled CPU_STOP# 3V66_1/VCH X 0 0 0
Description Reflects the value of FS0 pin sampled on power up Reflects the value of FS1 pin sampled on power up Reflects the value of FS2 pin sampled on power up Hardware mode: Reflects the value of PCI_STOP# pin sampled on PWD Software mode: 0=PCICLK stopped 1=PCICLK not stopped Reflects the current value of the external CPU_STOP# pin VCH Select 66MHz/48MHz 0=66MHz, 1=48MHz (Reser ved) 0=Spread Off, 1=Spread On
RW
Byte 1: Control Register
Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Pin# 52, 51 49, 48 45, 44 52, 51 49, 48 45, 44 43
Name CPUCLKT0 CPUCLKC0 CPUCLKT1 CPUCLKC1 CPUCLKT2 CPUCLKC2 CPUCLKT0 CPUCLKC0 CPUCLKT1 CPUCLKC1 CPUCLKT2 CPUCLKC2 MULTSEL0
PWD2 1 1 1 0 0 0 0 X
Type1 RW RW RW RW RW RW R
Description 0=Disabled 1=Enabled 4 0=Disabled 1=Enabled 4 0=Disabled 1=Enabled 4 Allow control of CPUCLKT0/C0 with asser tion of CPU_STOP# 0=Not free running 1=Free running Allow control of CPUCLKT1/C1 with asser tion of CPU_STOP# 0=Not free running 1=Free running Allow control of CPUCLKT2/C2 with asser tion of CPU_STOP# 0=Not free running 1=Free running (Reserved) Reflects the current value of MULTSEL0
Notes: 1. R= Read only RW= Read and Write 2. PWD = Power on Default 3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways. Wither the system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert PCI_STOP functionality via I2C Byte 0 Bit 3. In Hardware mode it is not allowed to write to the I2C Byte 0 Bit3. In Software mode it is not allowed to pull the external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped PCI_STOP conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it is not allowed to mix these modes. In Hardware mode the I2C byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip is in PCI_STOP mode. Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (I2C Byte 0 Bit 3 = 0)]. 4. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high, CPUCLKC off, and external resistor termination will bring CPUCLKC low.
0460G--08/31/04
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Integrated Circuit Systems, Inc.
ICS950201
Byte 2: Control Register
Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Pin# 10 11 12 13 16 17 18 -
Name PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 PCICLK6 -
PWD 1 1 1 1 1 1 1 0
Type RW RW RW RW RW RW RW -
Description 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled (Reserved)
Byte 3: Control Register
Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Pin# 5 6 7 5 6 7 39 38
Name PCICLK_F0 PCICLK_F1 PCICLK_F2 PCICLK_F0 PCICLK_F1 PCICLK_F2 48MHz_USB 48MHz_DOT
PWD 1 1 1 0 0 0 1 1
Type RW RW RW RW RW RW RW RW
Description 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled Allow control of PCICLK_F0 with asser tion of PCI_STOP#. 0=Free Running, 1=Not free running Allow control of PCICLK_F1 with asser tion of PCI_STOP#. 0=Free Running, 1=Not free running Allow control of PCICLK_F2 with asser tion of PCI_STOP#. 0=Free Running, 1=Not free running 0=Disabled 1=Enabled 0=Disabled 1=Enabled
Byte 4: Control Register
Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Pin# 21 22 23 24 35 33 -
Name 3V66-2 3V66-3 3V66-4 3V66_5 3V66_1/VCH_CLK 3V66_0 -
PWD 1 1 1 1 1 1 0 0
Type RW RW RW RW RW RW R R
Description 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled (Reserved) (Reserved)
Notes: 1. R= Read only RW= Read and Write 2. PWD = Power on Default
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5
Integrated Circuit Systems, Inc.
ICS950201
Byte 5: Programming Edge Rate (1 = enable, 0 = disable)
Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Pin# X X X X X X X X
Name 48MHz_USB 48MHz_USB 48MHz_DOT 48MHz_DOT -
PWD 0 0 0 0 0 0 0 0
Type RW RW RW RW -
Description USB edge rate cntrol USB edge rate cntrol DOT edge rate control DOT edge rate control (Reserved) (Reserved) (Reserved) (Reserved)
Byte 6: Vendor ID Register (1 = enable, 0 = disable)
Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Pin# X X X X X X X X
Name Vendor ID Bit0 Vendor ID Bit1 Vendor ID Bit2 Vendor ID Bit3 Revision ID Bit0 Revision ID Bit1 Revision ID Bit2 Revision ID Bit3
PWD 1 1 1 1 1 1 1 1
Type R R R R R R R R
Description (Reserved) (Reserved) (Reserved) (Reserved) Revision ID values will be based on individual device's revision
Notes: 1. R= Read only RW= Read and Write 2. PWD = Power on Default
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Integrated Circuit Systems, Inc.
ICS950201
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115C Storage Temperature . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage V DD = 3.3 V +/-5%
PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current IIL2 IDD3.3OP Operating Supply Current IDD3.3OP IDD3.3OP Powerdown Current Input Frequency Pin Inductance Input Capacitance1 Transition time Settling time1 Clk Stabilization1 Delay
1 1 1
SYMBOL CONDITIONS MIN VIH 2 VIL VSS - 0.3 IIH VIN = VDD -5 IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 VIN = 0 V; Inputs with pull-up resistors -200 CL = Full load; Select @ 100 MHz CL =Full load; Select @ 133 MHz CL = Full load; Select @ 200 MHz IREF=2.32 mA VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins To 1st crossing of target frequency From 1st crossing to 1% target frequency From VDD = 3.3 V to 1% target frequency 229 220 234
TYP
UNITS MAX V VDD + 0.3 V 0.8 5 A A
240 236 245 14.32
360 360 360 25 7 5 6 45 3 3 3 10 10
mA mA mA mA MHz nH pF pF pF ms ms ms ns ns
IDD3.3PD Fi Lpin CIN C OUT CINX Ttrans Ts
27
TSTAB tPZH,tPZL Output enable delay (all outputs) tPHZ,tPLZ Output disable delay (all outputs)
1 1
Guaranteed by design, not 100% tested in production.
0460G--08/31/04
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Integrated Circuit Systems, Inc.
ICS950201
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
TA = 0 - 70C; V DD = 3.3 V +/-5%; CL =2pF PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy SYMBOL Zo1 VHigh VLow Vovs Vuds Vcross(abs) d-Vcross ppm CONDITIONS VO = Vx Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. Variation of crossing over all edges see Tperiod min-max values 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 200MHz nominal 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, V OH = 0.525V V OH = 0.525V VOL = 0.175V MIN 3000 660 -150 -300 250 770 5 756 -7 350 12 -300 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 4.8735 5.8732 7.3728 9.8720 175 175 850 mV 150 1150 550 140 300 5.0015 5.0266 6.0018 6.0320 7.5023 5.4000 10.0030 10.0533 mV mV mV ppm ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps % ps ps 1 1 1 1 1 1,2 2 2 2 2 2 2 2 2 1,2 1,2 1,2 1,2 1 1 1 1 1 1 1 TYP MAX UNITS NOTES 1 1
Average period
Tperiod
Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle Skew Jitter, Cycle to cycle
1 2
Tabsmin tr tf d-tr d-tf dt3 tsk3 tjcyc-cyc
332 344 30 30 49 8 60
700 700 125 125 55 100 150
Measurement from differential wavefrom VT = 50% Measurement from differential wavefrom
45
Guaranteed by design, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz
0460G--08/31/04
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Integrated Circuit Systems, Inc.
ICS950201
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter,cycle to cyc
1
SYMBOL FO1 RDSP11 VOH
1
CONDITIONS VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 12 2.4 -33 30 0.5 0.5 45
TYP 33.33 33
MAX 55 0.55 -33 38
UNITS MHz V V mA mA ns ns % ps ps
VOL1 IOH IOL1
1
tr11 tf11 d t11 tsk11 tjcyc-cyc1
1.29 1.45 51 190 124
2 2 55 500 250
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL FO1 RDSP11 VOH1 VOL1 IOH1 IOL1 tr11 tf11 d t11 tsk11 tjcyc-cyc1 VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA
CONDITIONS
MIN 12 2.4
TYP 66.67 33
MAX UNITS MHz 55 0.55 V V mA mA ns ns % ps ps -33 38
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 3V66
-33 30 0.5 0.5 45 1.28 1.36 53.1 90 128
2 2 55 250 250
Guaranteed by design, not 100% tested in production.
0460G--08/31/04
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Integrated Circuit Systems, Inc.
ICS950201
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current 48DOT Rise Time 48DOT Fall Time VCH 48 USB Rise Time VCH 48 USB Fall Time Duty Cycle Jitter
1
SYMBOL FO1 RDSP11 V OH1 V OL1 IOH1 IOL1 tr11 tf11 tr11 tf11 dt11 tjcyc-cyc
1
CONDITIONS VO = V DD*(0.5) IOH = -1 mA IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, V OL @MAX = 0.4 V VOL = 0.4 V, V OH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VOL = 0.4 V, V OH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
MIN 20 2.4 -29 29 0.5 0.5 1 1 45
TYP MAX UNITS 48.008 MHz 60 0.4 -23 27 677 952 1.11 1.28 53 194 1 1 2 2 55 350 V V mA mA ns ns ns ns % ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
SYMBOL FO1 RDSP11 VOH1 VOL1 IOH1 IOL1 tr11 tf11 d t11 tjcyc-cyc1 VO = VDD*(0.5) IOH = -1 mA
CONDITIONS
MIN 20 2.4 -29 29 1 1 45
TYP 14.318 48
MAX 60 0.4 -23 27
UNITS MHz V V mA mA ns ns % ps
IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
1.25 1.21 52.2 675
2 2 55 1000
Guaranteed by design, not 100% tested in production.
0460G--08/31/04
10
Integrated Circuit Systems, Inc.
ICS950201
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
* * * * * * * * Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit
How to Write:
Controller (Host) Start Bit Address D2 (H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Stop Bit ICS (Slave/Receiver)
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
0460G--08/31/04
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Integrated Circuit Systems, Inc.
ICS950201
Un-Buffered Mode 3V66 & PCI Phase Relationship All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described below as Tpci.
3V66 (1:0) 3V66 (4:2) 3V66_5 PCICLK_F (2:0) PCICLK (6:0) Tpci
Group Skews at Common Transition Edges: (Un-Buffered Mode)
GROUP 3V66 PCI 3V66 to PCI
1
SYMBOL CONDITIONS 3V66 3V66 pin to pin skew PCI PCI_F and PCI pin to pin skew S3V66-PCI 3V66 leads 33MHz PCI
MIN 0 0 1.5
TYP
MAX UNITS 500 ps 500 ps 3.5 ns
Guaranteed by design, not 100% tested in production.
PD# Functionality
CPU_STOP# 1 0
CPUT Normal iref * Mult
CPUC Normal Float
3V66 66MHz Low
66MHz_OUT 66MHz_IN Low
PCICLK_F PCICLK 66MHz_IN Low
PCICLK 66MHz_IN Low
USB/DOT 48MHz 48MHz Low
0460G--08/31/04
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Integrated Circuit Systems, Inc.
ICS950201
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge. Assertion of PCI_STOP# Waveforms
PCI_STOP# PCI_F[2:0] 33MHz PCI[6:0] 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown. The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven. Assertion of CPU_STOP# Waveforms
CPU_STOP# CPUT CPUC
CPU_STOP# Functionality
CPU_STOP# 1 0
CPUT Normal iref * Mult
CPUC Normal Float
0460G--08/31/04
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Integrated Circuit Systems, Inc.
ICS950201
N
c
SYMBOL
L
INDEX AREA
E1
E
12 D h x 45
a
A A1 b c D E E1 e h L N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 18.31 18.55
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
A A1
-Ce
b SEATING PLANE .10 (.004) C
N 56
10-0034
D (inch) MIN .720 MAX .730
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS950201yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0460G--08/31/04
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Integrated Circuit Systems, Inc.
ICS950201
N
c
L
INDEX AREA
E1
E
12 D
a
A2 A1
A
In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS 0 8 0 8 aaa -0.10 -.004 VARIATIONS N 56
10-0039
-Ce
b SEATING PLANE
D mm. MIN 13.90 MAX 14.10 MIN .547
D (inch) MAX .555
aaa C
Reference Doc.: JEDEC Publication 95, MO-153
6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil)
Ordering Information
ICS950201yGLF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0460G--08/31/04
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Integrated Circuit Systems, Inc.
ICS950201
Revision History
Rev. G Issue Date Description 8/31/2004 Updated Lead Free information Page # 14-15
0460G--08/31/04
16

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